The present invention relates to the structure of a semiconductor device, in which a tape-like insulating member provided thereon with a number of wiring patterns and a number of electrode pads is bonded on a metal plate, semiconductor elements are mounted on the metal plate, the wiring patterns are electrically connected to electrodes of the semiconductor devices, and solder bumps are connected as external terminals to the electrode pads; and, more particularly, to a semiconductor device which has excellent connection reliability for the external terminals and excellent productivity in manufacturing it.
Recently, while high integration of semiconductor devices and providing a number of pins on semiconductor devices have progressed, a technique has been put into practical use for significantly increasing the number of pins (number of terminals) by changing the arrangement of the external terminals of a semiconductor package from the conventional linear arrangement, using leads to a two-dimensional arrangement using metal bumps. One of the specific structures is disclosed in the U.S. Pat. No. 5,216,278, in which semiconductor elements are mounted on one side of a printed circuit board and metal bumps are arranged on the other side thereof. This structure is generally called a BGA (ball grid array).
In addition, a semiconductor device has been developed for which the semiconductor package is reduced in size to as close to the dimensions of semiconductor element as possible. Such a semiconductor device is called a CSP (chip size package or chip scale package). Conventional CSP technology is, as disclosed in Japanese Patent Application Laid-Open Publication No. 6-504408 (WO92/05582), to manufacture a semiconductor device in which insulating tape with wiring patterns and external terminals is mounted onto a circuit formed surface of a semiconductor element through a flexible material, thereby electrically connecting the wiring patterns to electrodes of a semiconductor element. In addition, Japanese Patent Application Laid-Open Publication No. 6-224259 discloses a structure in which semiconductor elements are mounted onto a ceramic substrate with through holes, electrodes are provided on the other side of the ceramic substrate, and the ceramic substrate is mounted onto a printed circuit board. Moreover, Japanese Patent Application Laid-Open Publication No. 6-302604 discloses a CSP of a structure in which metal wiring patterns are formed on the circuit formed surface of a semiconductor element, and the metal wiring patterns are provided with external terminals.
Still further, Japanese Patent Application Laid-Open Publication No. 8-88293 discloses a semiconductor device of a structure in which insulating tape with wiring patterns and solder bumps (external terminals) is placed around a semiconductor element, and the wiring patterns are electrically connected to electrodes of the semiconductor element.
Among the above prior arts, the semiconductor device described in Japanese Patent Application Laid-Open Publication No. 8-88293, that is, the semiconductor device with the insulating tape around the semiconductor element, is of a structure enabling it to simultaneously attain a reduction of the size and provision of multiple pins. Since this structure uses the insulating taper for wiring, the wiring pattern can be finer than a printed circuit board, so that the pitch between the solder bumps as the external terminals can be reduced, and the external dimensions of the package can be made small. In addition, since the solder bumps are provided outside the semiconductor element, a larger number of bumps can be provided regardless of the size of semiconductor element.
However, the semiconductor device with the conventional structure described above has the following points which it is desirable to improve.
The first point is the productivity. Since this structure uses insulating tape with low rigidity, it is necessary to bond a metal plate on the other side of the insulating tape in order to reinforce it. Unless the metal plate is bonded, the flatness of the tape cannot be maintained, and a step is formed at the tip of a solder bump, thereby significantly deteriorating connection reliability. If separate metal plates are prepared for each semiconductor element to assure the connection reliability and are bonded to the insulating tape, it significantly hinders the productivity.
The second point to be improved is the flatness of the insulating tape. When separate metal plates are prepared and bonded to the insulating tape, as described above, there is a possibility that the adhesive may not be maintained for uniform thickness, or warpage caused by the roll habit of the insulating tape may not be eliminated. If the insulating tape has poor flatness, dispersion may be generated in the height of the bumps, which are the external terminals, thereby degrading connection reliability.
The object of the present invention is to provide a semiconductor device which overcomes the above disadvantages, and can improve the connection reliability of external terminals and productivity in manufacturing.
To attain this object, the present invention provides a semiconductor device comprising a semiconductor element, an insulating tape on a surface on which a number of wiring patterns and a number of electrode pads are formed, and a metal plate bonded to a reverse surface of the insulating tape by an adhesive.
The wiring patterns are electrically connected to electrodes of the semiconductor element, a number of solder bumps are connected to the electrode pads, at least a circuit formed surface of the semiconductor element is coated with a sealing resin, wherein at least one side wall of the device is a cut surface, and cut surfaces of the insulating tape, adhesive, and the metal plate on the side wall are aligned with each other.
In the semiconductor device according to the present invention arranged as above, at least one side wall of the device is a cut surface and cut surfaces of the insulating tape, adhesive, and the metal plate are aligned with each other. Such a structure is formed by bonding the insulating tape on a lead frame acting as the metal plate, loading a number of semiconductor elements on the lead frame, electrically connecting the wiring patterns provided on the insulating tape to the electrodes of the semiconductor elements, sealing a circuit formed surface of each semiconductor element with sealing resin, and then cutting the lead frame to simultaneously form a metal plate corresponding to each of the semiconductor elements. That is, when the lead frame is ultimately cut and divided into individual semiconductor devices, either side wall becomes a cut surface, and cut surfaces of the insulating tape, adhesive, and the metal plate are aligned with each other, so that flaws generated from cutting become a continuous state. As described, since the individual semiconductor devices are divided after they are formed on the lead frame, a plurality of semiconductor devices can be simultaneously produced, thereby significantly improving the productivity. In addition, since there are only two types of plate members which are simple in shape, that is, a lead frame and an insulating tape are first bonded, bonding can be easily performed in various manners such as a press or roller as the case may be. Adhesive can be applied in a uniform thickness. In addition, even if there is any warpage caused by the roll habit of the insulating tape, it is easy to eliminate such warpage. Therefore, it becomes possible to improve the flatness of the insulating tape, whereby connection reliability can be enhanced for the solder bumps as the external terminals.
Furthermore, while potting resin has been frequently used as a sealing resin, it has low productivity and causes wide dispersion in its shape after sealing, which may cause insufficient reliability after 15 sealing. On the other hand, according to the present invention, since the semiconductor devices are not yet divided into individual pieces at the time of sealing with resin, it is possible to use the transfer mold process which is used for a conventional leaded package. This also enhances the productivity and the reliability of the sealing.
The metal plate of the semiconductor device as described above preferably comprises an element mount for mounting a semiconductor element, and an insulating tape mount positioned around the element mount and for mounting the insulating tape, wherein a top surface of the element mount is positioned at a lower position than a surface of the insulating tape mount and the element mount and the insulating tape mount are connected by connecting steps starting from outside of a boundary between the element mount and the insulating tape mount, and extending to an outer periphery of the element mount.
Since the top surface of the element mount is positioned at a lower position than the surface of the insulating tape mount, as described above, it becomes possible to prevent the semiconductor element from extending beyond the top surface of the insulating tape. It is necessary to secure the semiconductor while performing wire bonding, as will be described later. In this case, the semiconductor element is mounted on and secured to the element mount which is a part of the metal plate, and therefore, wire bonding can be stably and reliably carried out.
In the above, at least a part of an outer periphery of the metal plate may extend beyond an outer periphery of the insulating tape. In addition, in this case, projecting leads integral with the metal plate and projecting to the height of the solder bump may be provided on at least a part of the metal plate extending beyond the outer periphery of the insulating tape. Provision of such projecting leads enables the projecting leads integral with the metal plate to be connected to the ground of a printed circuit board upon mounting on the printed circuit board, whereby electrical noise generated in the semiconductor device can be reduced, and a semiconductor element with a higher operating frequency can be mounted. In addition, since a heat dissipation path is formed from the semiconductor element to the printed circuit board through the sealing resin, the metal plate, and the projecting leads, heat generated in the semiconductor element can be efficiently dissipated, thereby making it possible to reduce thermal resistance and to mount a semiconductor element with high heat generation.
When the tape automated bonding which is used in the tape carrier package is used in connecting the wiring pattern and the electrodes of the semiconductor element, a special manufacturing apparatus is required, and it is necessary to prepare the tape for each semiconductor element because the wiring pattern has no degree of freedom regarding the electrodes of the semiconductor element. However, according to the present invention, since the other side of the insulating tape has been bonded with the lead frame with high rigidity, when the electrodes of the semiconductor element are connected to the wiring pattern, the wiring pattern is also made rigid, so that they can be connected by a wire bonding process with higher connection reliability. That is, according to the present invention, it is preferable to use a metal wire for the electrical connection of the wiring pattern and the electrodes of the semiconductor element with the wire bonding process.
However, if wire bonding is not employed, the electrical connection between the wiring pattern and the electrodes of the semiconductor element may be performed by using the tape automated bonding.
In addition, it is also preferable that the insulating tape for connection to the lead frame is one continuous tape, common to each of the semiconductor elements. This eliminates the necessity to prepare an insulating tape for each semiconductor element, and also to individually bond the insulating tape, so that the productivity is further enhanced.
In addition, the present invention provides a lead frame for a semiconductor device which comprises a plurality of semiconductor loading sections for loading a plurality of semiconductor elements, and a plurality of devices being constituted by loading each of the semiconductor elements in the semiconductor loading section, wherein a plurality of insulating tape provided with a number of wiring patterns and a number of electrode pads at positions corresponding to each of the semiconductor element loading sections are bonded through adhesive provided on the opposite surface to the surface with the wiring patterns.
Alternately, instead of bonding a plurality of insulating tapes on the lead frame as described above, insulating tape may be one continuous tape, common to each of the semiconductor elements, provided with a number of wiring patterns and a number of electrode pads at positions corresponding to each of the semiconductor element loading sections, and bonded through adhesive provided on the opposite surface to the surface with the wiring patterns.